

The linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R′ i=R′ i-1R′ i-1R′ i-1R′ i-1, and the permutation code forms, with an additional bit, a thirteen bit address. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol.
